In recent years, multichip packaging has been predominantly used in the field of semiconductor device packaging. Along with this trend, development efforts have been directed to 2.5-D packaging technology utilizing silicon interposers, silicon bridges, fine resin interposers or the like as well as 3-D packaging technology utilizing silicon interposers or glass interposers.
2.5-D packaging, however, connects chips with each other through planar interconnections, which results in the need to lay out a large number of interconnections within a limited area. Formation of fine interconnections may be needed for such purposes, which may result in a complex structure and complicated manufacturing steps. Lengthy interconnections having short intervals connect between chips. Such an arrangement may cause interference and the like between signal lines, thereby creating an adverse effect on the transmission characteristics.
3-D packaging technology provides penetrating electrodes through silicon interposers and glass interposers to achieve the shortest-distance connections between chips. Forming penetrating electrodes, however, involves high cost, which hinders the spread of their use. Further, silicon interposers use semiconductor for the base substrate thereof, thereby causing parasitic LCR to be created between interconnection patterns and the substrate. This causes degradation in high-speed signal characteristics. The use of glass interposers serves to avoid the effect of parasitic impedances, but forming penetrating electrodes at narrow pitches through glass interposers is more difficult than in the case of silicon interposers. There is also the problem of higher thermal resistance.
There is a 3-D packaging technology that mounts a chip on an interconnection layer formed on a silicon support base, and removes the support base, followed by using the interconnection layer for connections with chips on both faces thereof. This technology does not involve the formation of penetrating electrodes, and utilizes the vias of the interconnection layer to connect between the chips. With this arrangement, thus, the problem of high process cost for providing penetrating electrodes through silicon interposers and glass interposers do not exist.
The above-noted technology uses silicon as the support base, and the removal of such a support base complicates the production steps.
Accordingly, it may be desirable to provide a semiconductor device that has a plurality electronic components arranged in the thickness direction thereof, and that is produced by simple production steps.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2008-141061